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Synplicity - http://www.synplicity.com/
Logic synthesis and verification products for FPGA and ASIC designers. |
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Verilog Dot Com - http://www.verilog.com/
Verilog resources page. Includes FAQ, books and links. Also verilog aware Emacs add on. |
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http://www.aldec.com/ - http://www.aldec.com/
HDL design entry and simulation software for programmable logic designers. |
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Doulos Ltd - http://www.doulos.com/
Training and consultancy across Europe in VHDL, Verilog, SystemC, Perl and Tcl/Tk. Offers free resources for hardware designers. |
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Green Mountain - http://www.gmvhdl.com/
VHDL compilers and design environments, including Windows, DOS and Linux support. |
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CAST, Inc. - http://www.cast-inc.com/
Provides a broad line of general purpose IP cores for electronic design (also called silicon intellectual property, SIP, or virtual components, VCs). Includes processors, bus and network interfaces, multimedia and encryption functions, serial communications, and peripheral controllers. |
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Symphony EDA - http://www.symphonyeda.com/
Offers a VHDL compiler/simulator with an integrated development environment. Supports VHDL'93, Vital, and SDF. Free command-line tools also available. |
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http://www.saros.co.uk/ - http://www.saros.co.uk/
Offering a full suite of VHDL and Verilog design tools, from design-entry, simulation and synthesis to verification and training. |
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TimingTool - Online timing diagram editor - http://www.timingtool.com/
Free to use online timing diagram editor. Timing diagrams are saved in TDML format. Translators from TDML to DXF, VHDL, and Verilog are also supplied. |
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Translogic - http://www.translogiccorp.com/
EASE and EALE provide HDL aware entry tools, both graphical and text based. Also providing Linux support. |
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Experimental Computing Laboratory - http://www.ece.uc.edu/~paw/
Includes papers, presentations, conference publications and SAVANT VHDL, a free VHDL analyser and simulator. From University of Cincinnati. |
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http://www.imodl.com/ - http://www.imodl.com/
The iValidate toolset comprises ready-to-use functional verification tools and simulation models. |
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Sutherland HDL, Inc. - http://www.sutherland-hdl.com/
Provides Verilog HDL and Verilog PLI training workshops and consulting services. |
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http://www.esperan.com/ - http://www.esperan.com/
VHDL, Verilog and FPGA training courses held in the US, Europe and the UK. |
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Calyptech Design Services - http://www.calyptech.com/
Offers ASIC and FPGA design and verification services, drivers and tools. Includes product and service overview and PDF detailed product specifications available. |
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SynaptiCAD - http://www.syncad.com/
Provides Verilog, VHDL, TDML, logic analyzer, pattern generator, and SPICE tools. |
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Freeware Verilog & VHDL - http://www.v-ms.com/
This is the home page for a Freeware Verilog,VHDL and Analog Mixed Signal project (a.k.a. the V-2000 project, still in its infancy). |
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Exemplar Logic, Inc. - http://www.exemplar.com/
Provides LeonardoSpectrum which is a CPLD, FPGA and desktop ASIC synthesis solution. |
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Time Rover - http://www.time-rover.com/
Provides tools for aiding Verilog development. Including The Temporal Rover for automatic verification of protocols and Verilog Java PLI. |
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Rajesh Verilog FAQ - http://www.angelfire.com/in/rajesh52/verilog.html
General Verilog resource that includes a FAQ, tutorials, and commercial information. |
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eXsultation - http://www.exsultation.com/
Specialize in full turn-key, customer facility training programs in VHDL, Verilog,C++ modeling, formal verification, and FPGA design. |
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Sandstrom Engineering - http://www.sandstrom.org/about.htm
HDL pre-synthesis tools which check code for synthesizability. Then suggest replacement code where problems are found. |
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Nova Engineering - http://www.nova-eng.com/vhdl.html
Megafunctions are modular, DSP algorithms and functional blocks for custom use in PLD or ASIC designs. |
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The Hamburg VHDL Archive - http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html
A collection of public-domain or shareware, VHDL documentation, models, and tools. |
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Verilog-AMS - http://www.eda-stds.org/verilog-ams/
The Verilog-AMS Technical Subcommittee has been created with the charter to develop, update and promote analog and mixed signal extensions to the Verilog (IEEE-1364) language. |