  |
http://www.jhdl.org/ - http://www.jhdl.org/
JHDL is a method of describing (programmatically, in JAVA) the components and connections in a digital logic circuit. |
| |
http://www.myhdl.org/ - http://www.myhdl.org/
Python package for using Python as a hardware description and verification language. |
| |
Perlilog - http://www.opencores.org/projects.cgi/web/perlilog/overview
As the name implies, Perilog uses a mix of Perl and Verilog to construct parametric hardware designs. |
| |
Hydra Computer HDL - http://www.dcs.gla.ac.uk/~jtod/Hydra/
Hydra is an HDL based on the functional programming language Haskell. |
| |
http://rhdl.rubyforge.org/ - http://rhdl.rubyforge.org/
RHDL (Ruby Hardware Description Language) is an HDL based on the Ruby programming language. |