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Stack Computers & Forth - http://www.ece.cmu.edu/~koopman/stack.html
Philip J. Koopman, Jr., CMU page. Reports, studies, and links. Compares: CISC, RISC, Stack systems; 2 and 3 stack systems. |
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Wikipedia: One Instruction Set Computer - http://en.wikipedia.org/wiki/One_instruction_set_computer
Online encyclopedia article about this single machine language opcode, with links to related articles. |
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MOVE Project - http://ce-serv.et.tudelft.nl/MOVE/
Automatic Synthesis of Application Specific Processors. Goal: design, build high-performance processors via a new class of transport-triggered architectures, TTAs, programmed by specifying data-transports not operations; well suited for application specific uses. |
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4stack Processor - http://www.jwdt.com/~paysan/4stack.html
Research project for high performance, low cost computing. Uses stack-based instructions for a 4-way VLIW processor. Implemented in current technology, it would outrun high-end DSPs (TMS 320C6x, TigerSHARC), and let the full program run on one processor, with no further RISC core. |
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New Micros, Inc. - http://www.newmicros.com/
Designs, builds: single board computers (SBC), peripherals, embedded systems, PCB design/layout, high level programming (industry leaders in Forth), custom design work; large line of stock products: from full handheld computers to development packages. Since 1980. |
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Wikipedia: Transport Triggered Architectures - http://en.wikipedia.org/wiki/Transport_Triggered_Architectures
Online encyclopedia article about this approach to computer architecture. |
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PTSC: Patriot Scientific Corp. - http://www.ptsc.com/
Makes IGNITE I ROSC (Removed Operand Set Computer), PSC1000 32-bit embedded shBoom-based microprocessor line, many ISDN interface products, sophisticated antenna/radar technologies. |
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Java Optimized Processor - http://www.jopdesign.com/
JOP is the implementation of a small java processor with the JVM fitting in a FPGA. |
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NASA: Space Related Applications of Forth - http://forth.gsfc.nasa.gov/
Uses of Forth microprocessors and programming language: controllers for spacecraft flight systems, on-board payload experiments, ground support; hardware or software to build or test flight or ground systems. |
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The Ultimate RISC - http://www.cs.uiowa.edu/~jones/arch/risc/
Explains extreme, simple RISC, with only one instruction, move memory to memory; yet it is useful. Revision of paper first published in ACM Computer Architecture News. |
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Forth Chips - http://www.ultratechnology.com/chips.htm
References, links to Forth and stack machines in various technologies. |
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Triangle Digital Services Ltd. - http://www.triangledigital.com/
Small, powerful Forth embedded computers: let you quickly design applications: controls, portable instruments, terminals, data loggers, GPS, CAN bus, multitasking, LCD and keyboard systems. High level language makes development simple and fast; needs no PROM programmer. Forth hardware and software. |
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SandPiper Technology - http://www.sandpipers.com/
Course on minimal processors: Guided Exploration of two FPGA-based CPU Designs, led by John Rible. |
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Microprocessor Architectures from VLIW to TTA - http://www.ics.ele.tue.nl/~heco/documents/TTAbook/TTAbook.html
By Henk Corporaal; John Wiley, 1998, ISBN 047197157X. Introduces Transport Triggered Architectures, TTAs. In standard architectures, programmed operations trigger internal data transports. TTAs work by programming data transports themselves. This removes bottlenecks, allows for new code generation optimizations, uses hardware more efficiently. |
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Minimal Instruction Set Computers - http://www.ultratechnology.com/misc.html
Stack-based processors, 5-bit words, 25 instructions, 7000 transistors, 80 MIPS, 50 milliwatts, low cost; designed by Chuck Moore, creator of Forth programming language. |
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MSL16 Processor - http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/old/msl16/msl16.html
Minimal instruction set, small, low power 16-bit CPU optimized to run Forth on a Xilinx FPGA. When system is stable, VHDL source code for CPU and all other code will be released to make a full open source public domain CPU. |
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Enumera, Inc. - http://www.enumera.com/
Goal: dominate very low cost, low power, single core CPU market, and have the only ultra-high-end supercomputer on-a-chip system. Because the CPU core is so small, it is possible to put 1000s of cores and memory in one IC chip package. |
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T-Recursive Technology - http://www.zetetics.com/recursiv/capabil.htm#Hardware
Embedded systems consultant for small (8/16-bit) and distributed microprocessor systems. Contract hardware and software development for most microcontrollers. Specialist: Forth, Assembly, C. By Bradford J. Rodriguez, Ph.D. |
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E25 Computer Architecture: Lab 5: OISC: One Instruction Set Computer - http://www.sccs.swarthmore.edu/users/06/adem/engin/e25/finale/
Class project to design and implement One Instruction Set Computer; using instruction: SUBLEQ A B C. Meaning: subtract value in M(A) from M(B) and store it in M(B), if result is not positive, go to instruction C. Descriptions, diagrams, code, tables. |
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A No Instruction Set Processor - http://www.cowlark.com/nisc.html
Benefits: simple, easily pipelined, useful in self-clocked systems, very flexible and optimizable, good memory access, highly. Problems: awkward to program. [cowlark.com] |